book/VHDL을 이용한 FPGA 디지털 설계
'1' 개수 카운터
쿨한넘
2014. 6. 25. 23:09
--
-- VHDL을 이용한 FPGA 설계
--
-- 3장. Section08. '1' 개수 카운터
--
library ieee;
use ieee.std_logic_1164.all;
entity OneCounter is
port (
d : in std_logic_vector (7 downto 0);
seg : out std_logic_vector (6 downto 0)
);
end OneCounter;
architecture arc of OneCounter is
-- convert integer value to drive 7-segment
--
function toSeg(
in_value : in integer range 0 to 15
) return std_logic_vector is
begin
case in_value is
when 0 => return "1000000";
when 1 => return "1111001";
when 2 => return "0100100";
when 3 => return "0110000";
when 4 => return "0011001";
when 5 => return "0010010";
when 6 => return "0000010";
when 7 => return "1011000";
when 8 => return "0000000";
when 9 => return "0011000";
when 10 => return "0001000";
when 11 => return "0000011";
when 12 => return "0100111";
when 13 => return "0100001";
when 14 => return "0000110";
when 15 => return "0001110";
when others => return "1111111";
end case;
end toSeg;
begin
process (d)
variable oneCount : integer;
begin
oneCount := 0;
for i in d'range loop
if d(i) = '1' then
oneCount := oneCount + 1;
end if;
end loop;
seg <= toSeg(oneCount);
end process;
end arc;