전감산기의 설계

D = (X - Bi) - Y

Bi는 아래 자리에 빌려준 값. 입력이 된다.

위에서 빌린 수는 B로 표현되고, 진리표를 작성해보면 쉽다.

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-- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;     entity FullSubtractor_vhdl is       port (         X, Y, bi    :   in  integer range 0 to 1;         D, B        :   out std_logic     );   end FullSubtractor_vhdl;     architecture arc of FullSubtractor_vhdl is       signal  diff    :   integer range -2 to 1;   begin       process(X, Y, bi)     begin               diff <= X - bi - Y;                   if diff = -2 then       -- XYbi = 011               D   <=   '0';             B   <=   '1';                       elsif diff = -1 then    -- XYbi = 001, 010, 111                       D   <=   '1';             B   <=   '1';                       elsif diff = 0 then     -- XYbi = 000, 101, 110                       D   <=   '0';             B   <=   '0';                       else                    -- XYbi = 100                       D   <=   '1';             B   <=   '0';                       end if;             end process;     end arc;