7-segment decoder

4bit 스위치 입력을 받아 7 세그먼트에 표시한다.

DE2-115에 맞게 바꿔었다.

numeric_std 을 사용하기 위해서는 std_logic_arith 을 인클루드 하지 말아야.

http://www.lothar-miller.de/s9y/uploads/Bilder/Usage_of_numeric_std.pdf 참조.

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-- -- VHDL을 이용한 FPGA 디지털 설계 -- section_03 Lab4 7-segment decoder --   library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all;     entity Lab4_7seg is       port (         CLOCK_50        :   in      std_logic;         SW              :   in      std_logic_vector (17 downto 0);         HEX0            :   out     std_logic_vector (6 downto 0)     );       end Lab4_7seg;     architecture arc of Lab4_7seg is       signal  keyVal      :   integer range 0 to 15;   begin         keyVal <= to_integer(unsigned(SW (3 downto 0)) );         process (CLOCK_50)     begin               if rising_edge(CLOCK_50) then                       case keyVal is                                         --  "gfedcba"                 when 0      =>   HEX0    <=   "1000000";                 when 1      =>   HEX0    <=   "1111001";                 when 2      =>   HEX0    <=   "0100100";                 when 3      =>   HEX0    <=   "0110000";                 when 4      =>   HEX0    <=   "0011001";                 when 5      =>   HEX0    <=   "0010010";                 when 6      =>   HEX0    <=   "0000010";                 when 7      =>   HEX0    <=   "1011000";                 when 8      =>   HEX0    <=   "0000000";                 when 9      =>   HEX0    <=   "0011000";                 when 10     =>   HEX0    <=   "0001000";                 when 11     =>   HEX0    <=   "0000011";                 when 12     =>   HEX0    <=   "0100111";                 when 13     =>   HEX0    <=   "0100001";                 when 14     =>   HEX0    <=   "0000110";                 when 15     =>   HEX0    <=   "0001110";                 when others =>   null;               end case;               end if;               end process;   end arc;