lab06. 수의 정렬회로 설계

...

--
-- VDHL을 이용한 FPGA 설계
--
-- 3장 Lab06. 수의 정렬 회로 설계
--
--	de2-115 로 구현.
--		input a 	=>	SW17~SW14
--		input b 	=>	SW3~SW0
--		value a		=>	HEX6
--		value b 	=>	HEX4
--		value max 	=>	HEX3
--		value min 	=>	HEX0
--		input ena	=>	KEY0
--
package my_package is

	constant input_width	:	integer := 4;
	constant output_width	:	integer := 4;
	
	subtype input_value		is integer range 0 to 2**input_width - 1;
	subtype output_value	is integer range 0 to 2**output_width - 1;
	
end my_package;


library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;


entity lab06 is

	port (
		a		:	in		input_value;
		b		:	in		input_value;
		ena		:	in		std_logic;

		led_a	:	out		std_logic_vector (6 downto 0);
		led_b	:	out		std_logic_vector (6 downto 0);
		
		led_max	:	out		std_logic_vector (6 downto 0);
		led_min	:	out		std_logic_vector (6 downto 0)

	);
	
end lab06;


architecture arc of lab06 is

	signal	max		:	output_value;
	signal	min		:	output_value;

	-- convert integer value to drive 7-segment
	--
	function to_hex(
		in_value	:	in	input_value
	) return std_logic_vector is
	begin
	
		case in_value is
		
			when 0	 	=>	return "1000000";
			when 1		=>	return "1111001";
			when 2		=>	return "0100100";
			when 3		=>	return "0110000";
			when 4		=>	return "0011001";
			when 5		=>	return "0010010";
			when 6		=>	return "0000010";
			when 7		=>	return "1011000";
			when 8		=>	return "0000000";
			when 9		=>	return "0011000";
			when 10		=>	return "0001000";
			when 11		=>	return "0000011";
			when 12		=>	return "0100111";
			when 13		=>	return "0100001";
			when 14		=>	return "0000110";
			when 15		=>	return "0001110";
			when others	=>	return "1111111";

		end case;
			
	end to_hex;
		
begin


	led_a	<=	to_hex(a);
	led_b	<=	to_hex(b);
	led_max	<=	to_hex(max);
	led_min	<=	to_hex(min);


	process (a, b, ena)
	begin
	
		if (ena = '0') then
		
			if (a > b) then
			
				max	<=	a;
				min	<=	b;
			
			else
			
				max	<=	b;
				min	<=	a;

			end if;
			
		end if;

	end process;
		
	
end arc;