xor을 이용한 전감산기 설계

뭐...

library ieee;
use ieee.std_logic_1164.all;


entity FullSubtractor_xor_vhdl is

	port (
		x, y, z		:	in		std_logic;
		D, B		:	out		std_logic
	);

end FullSubtractor_xor_vhdl;


architecture arc of FullSubtractor_xor_vhdl is
begin

	D	<=	x xor y xor z;
	B	<=	((not (x xor y)) and z) or ((not x) and y);
	
end arc;