잡다한 인생

	// Get Greatest Common Divider (GCD)
	// using Euclid's algorithm
	//
	// while (a != b) {
	//	if (a > b)
	//		a = a - b;
	//	else
	//		b = b - a;
	// }

	.global	example8_5
	.global	gcd

example8_5:
gcd:
	cmp  	r0, r1
	subgt	r0, r1			// if r0 > r1, r0 -= r1
	sublt	r1, r0			// if r0 < r1, r1 -= r0
	bne	gcd

	bx  	lr			// if r0 == r1, return

	.end

/*
   Capacitive touch sensor demo
*/

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#include <avr/power.h>
#include "pinDefines.h"
#include "USART.h"


#define SENSE_TIME   25
#define THRESHOLD    8000


// -------  Global Variables ---------- //

volatile uint16_t chargeCycleCount;


// ------- Functions -------- //

void initPinChangeInterrupt(void)
{
	PCICR |= (1 << PCIE1);	/* enable Pin-change interrupts 1 (bank C) */
	PCMSK1 |= (1 << PC1);	/* enable specific interrupt for our pin PC1 */
}


ISR (PCINT1_vect)
{
	chargeCycleCount++;	/* count this change */

	CAP_SENSOR_DDR |= (1 << CAP_SENSOR);	/* output mode */
	_delay_us(1);				/* charging delay */

	CAP_SENSOR_DDR &= ~(1 << CAP_SENSOR);	/* set as input */
	PCIFR |= (1 << PCIF1);			/* clear the pin-change interrupt */
}


int main(void)
{
	// -------- Inits --------- //
	clock_prescale_set(clock_div_1);	/* full speed */
	initUSART();
	printString("==[ Cap Sensor ]==\r\n\r\n");


	LED_DDR = 0xff;
	MCUCR |= (1 << PUD);			/* disable all pull-ups */
	CAP_SENSOR_PORT |= (1 << CAP_SENSOR);	/* we can leave output high */

	initPinChangeInterrupt();


	// ------ Event loop ------ //
	while (1) {

		chargeCycleCount = 0;		/* reset counter */
		CAP_SENSOR_DDR |= (1 << CAP_SENSOR);	/* start with cap charged */

		sei();				/* start up interrupts, counting */
		_delay_ms(SENSE_TIME);
		cli();				/* done */

		if (chargeCycleCount < THRESHOLD) {
			LED_PORT = 0xff;
		} else {
			LED_PORT = 0;
		}

		printWord(chargeCycleCount);	/* for fine tuning */
		printString("\r\n");

	}	/* End event loop */

	return (0);				/* This line is never reached */
}

--
--	VHDL을 이용한 FPGA 설계
--
--	3장. Section08. '1' 개수 카운터
--
library ieee;
use ieee.std_logic_1164.all;


entity OneCounter is

	port (
		d		:	in		std_logic_vector (7 downto 0);
		seg		:	out		std_logic_vector (6 downto 0)
	);
	
end OneCounter;


architecture arc of OneCounter is

    -- convert integer value to drive 7-segment
    --
    function toSeg(
        in_value    :   in  integer range 0 to 15
    ) return std_logic_vector is
    begin
     
        case in_value is
         
            when 0      =>   return "1000000";
            when 1      =>   return "1111001";
            when 2      =>   return "0100100";
            when 3      =>   return "0110000";
            when 4      =>   return "0011001";
            when 5      =>   return "0010010";
            when 6      =>   return "0000010";
            when 7      =>   return "1011000";
            when 8      =>   return "0000000";
            when 9      =>   return "0011000";
            when 10     =>   return "0001000";
            when 11     =>   return "0000011";
            when 12     =>   return "0100111";
            when 13     =>   return "0100001";
            when 14     =>   return "0000110";
            when 15     =>   return "0001110";
            when others =>   return "1111111";
 
        end case;
             
    end toSeg;

begin


	process (d)

		variable oneCount	:	integer;
		
	begin
	
	
		oneCount	:=	0;
		
		for i in d'range loop
		
			if d(i) = '1' then
				oneCount	:=	oneCount + 1;
			end if;
			
		end loop;
		
		seg		<=	toSeg(oneCount);


	end process;


end arc;

--
--	VHDL을 이용한 FPGA 설계
--	3장. section07. n비트 가산 / 감산기
--		DE2-117 구현
--
library ieee;
use ieee.std_logic_1164.all;

package my_package is

	constant	adder_width		:	integer := 4;
	constant	result_width	:	integer := 5;
	constant	max_result		:	integer := 2**result_width - 1;
	constant	min_result		:	integer := -2**result_width;
	
	subtype		adder_value		is	integer range 0 to 2**adder_width - 1;
	subtype		result_value	is	integer range min_result to max_result;
	
end my_package;


library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;

entity nbitAddSub is

	port (
		a, b		:	in		adder_value;
		mode		:	in		std_logic;
		sega		:	out		std_logic_vector (6 downto 0);	-- hex6 of de2-117
		segb		:	out		std_logic_vector (6 downto 0);	-- hex4 of de2-117
		segmode		:	out		std_logic_vector (6 downto 0);	-- hex3 of de2-117
		segsign		:	out		std_logic;						-- hex2 of de2-117
		seg1		:	out		std_logic_vector (6 downto 0);	-- hex0 of de2-117
		seg2		:	out		std_logic_vector (6 downto 0);	-- hex1 of de2-117
		underflow	:	out		std_logic;
		overflow	:	out		std_logic
	);
	
end nbitAddSub;


architecture arc of nbitAddSub is

	signal	over, under	:	std_logic;
	signal	seg1Reg, seg2Reg	:	integer range 0 to 15;


	-- convert integer value to drive 7-segment
	--
	function toSeg(
		in_value	:	in	integer range 0 to 15
	) return std_logic_vector is
	begin
	
		case in_value is
		
			when 0	 	=>	return "1000000";
			when 1		=>	return "1111001";
			when 2		=>	return "0100100";
			when 3		=>	return "0110000";
			when 4		=>	return "0011001";
			when 5		=>	return "0010010";
			when 6		=>	return "0000010";
			when 7		=>	return "1011000";
			when 8		=>	return "0000000";
			when 9		=>	return "0011000";
			when 10		=>	return "0001000";
			when 11		=>	return "0000011";
			when 12		=>	return "0100111";
			when 13		=>	return "0100001";
			when 14		=>	return "0000110";
			when 15		=>	return "0001110";
			when others	=>	return "1111111";

		end case;
			
	end toSeg;

begin


	process (mode, a, b, over, under)
		variable res	:	result_value;
	begin

		if (mode = '1') then		-- if key0 is not pressed
			res		:=	a + b;
			segmode	<=	toSeg(10);	-- display 'A' for mode add
		else
			res		:=	a - b;
			segmode	<=	toSeg(5);	--	display 'S' for mode subtraction
		end if;

	
		if (res > max_result) then
			over	<=	'1';
		else
			over	<=	'0';
		end if;


		if (res < min_result) then
			under	<=	'1';
		else
			under	<=	'0';
		end if;


		if (res < 0) then
			segsign	<=	'0';		-- turn on minus sign
			seg2Reg	<=	-res / 16;
			seg1Reg	<=	-res mod 16;
		else
			segsign	<=	'1';		-- turn off minus sign
			seg2Reg	<=	res / 16;
			seg1Reg	<=	res mod 16;
		end if;

		overflow	<=	over;
		underflow	<=	under;

	end process;


	sega	<=	toSeg(a);
	segb	<=	toSeg(b);
	seg1	<=	toSeg(seg1Reg);
	seg2	<=	toSeg(seg2Reg);

	
end arc;

--
-- VDHL을 이용한 FPGA 설계
--
-- 3장 Lab06. 수의 정렬 회로 설계
--
--	de2-115 로 구현.
--		input a 	=>	SW17~SW14
--		input b 	=>	SW3~SW0
--		value a		=>	HEX6
--		value b 	=>	HEX4
--		value max 	=>	HEX3
--		value min 	=>	HEX0
--		input ena	=>	KEY0
--
package my_package is

	constant input_width	:	integer := 4;
	constant output_width	:	integer := 4;
	
	subtype input_value		is integer range 0 to 2**input_width - 1;
	subtype output_value	is integer range 0 to 2**output_width - 1;
	
end my_package;


library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;


entity lab06 is

	port (
		a		:	in		input_value;
		b		:	in		input_value;
		ena		:	in		std_logic;

		led_a	:	out		std_logic_vector (6 downto 0);
		led_b	:	out		std_logic_vector (6 downto 0);
		
		led_max	:	out		std_logic_vector (6 downto 0);
		led_min	:	out		std_logic_vector (6 downto 0)

	);
	
end lab06;


architecture arc of lab06 is

	signal	max		:	output_value;
	signal	min		:	output_value;

	-- convert integer value to drive 7-segment
	--
	function to_hex(
		in_value	:	in	input_value
	) return std_logic_vector is
	begin
	
		case in_value is
		
			when 0	 	=>	return "1000000";
			when 1		=>	return "1111001";
			when 2		=>	return "0100100";
			when 3		=>	return "0110000";
			when 4		=>	return "0011001";
			when 5		=>	return "0010010";
			when 6		=>	return "0000010";
			when 7		=>	return "1011000";
			when 8		=>	return "0000000";
			when 9		=>	return "0011000";
			when 10		=>	return "0001000";
			when 11		=>	return "0000011";
			when 12		=>	return "0100111";
			when 13		=>	return "0100001";
			when 14		=>	return "0000110";
			when 15		=>	return "0001110";
			when others	=>	return "1111111";

		end case;
			
	end to_hex;
		
begin


	led_a	<=	to_hex(a);
	led_b	<=	to_hex(b);
	led_max	<=	to_hex(max);
	led_min	<=	to_hex(min);


	process (a, b, ena)
	begin
	
		if (ena = '0') then
		
			if (a > b) then
			
				max	<=	a;
				min	<=	b;
			
			else
			
				max	<=	b;
				min	<=	a;

			end if;
			
		end if;

	end process;
		
	
end arc;

--
-- VHDL을 이용한 FPGA 디지털 설계
-- section_03 Lab4 7-segment decoder
--

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;


entity Lab4_7seg is

	port (
		CLOCK_50		:	in		std_logic;
		SW				:	in		std_logic_vector (17 downto 0);
		HEX0			:	out		std_logic_vector (6 downto 0)
	);
	
end Lab4_7seg;


architecture arc of Lab4_7seg is

	signal	keyVal		:	integer range 0 to 15;

begin


	keyVal <= to_integer(unsigned(SW (3 downto 0)) );


	process (CLOCK_50)
	begin
	
		if rising_edge(CLOCK_50) then
		
			case keyVal is
										--	"gfedcba"
				when 0		=>	HEX0	<=	"1000000";
				when 1		=>	HEX0	<=	"1111001";
				when 2		=>	HEX0	<=	"0100100";
				when 3		=>	HEX0	<=	"0110000";
				when 4		=>	HEX0	<=	"0011001";
				when 5		=>	HEX0	<=	"0010010";
				when 6		=>	HEX0	<=	"0000010";
				when 7		=>	HEX0	<=	"1011000";
				when 8		=>	HEX0	<=	"0000000";
				when 9		=>	HEX0	<=	"0011000";
				when 10		=>	HEX0	<=	"0001000";
				when 11		=>	HEX0	<=	"0000011";
				when 12		=>	HEX0	<=	"0100111";
				when 13		=>	HEX0	<=	"0100001";
				when 14		=>	HEX0	<=	"0000110";
				when 15		=>	HEX0	<=	"0001110";
				when others	=>	null;

			end case;
	
		end if;
		
	end process;

end arc;

library ieee;
use ieee.std_logic_1164.all;


entity FullSubtractor_xor_vhdl is

	port (
		x, y, z		:	in		std_logic;
		D, B		:	out		std_logic
	);

end FullSubtractor_xor_vhdl;


architecture arc of FullSubtractor_xor_vhdl is
begin

	D	<=	x xor y xor z;
	B	<=	((not (x xor y)) and z) or ((not x) and y);
	
end arc;

library ieee;
use ieee.std_logic_1164.all;


entity FullAdder_xor_vhdl is

	port (
		x, y, z		:	in		std_logic;
		S, C		:	out		std_logic
	);
	
end FullAdder_xor_vhdl;


architecture arc of FullAdder_xor_vhdl is
begin

	S	<=	x xor y xor z;
	C	<=	(z and (x xor y)) or (x and y);
	
end arc;

--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity FullSubtractor_vhdl is

	port (
		X, Y, bi	:	in	integer range 0 to 1;
		D, B		:	out	std_logic
	);

end FullSubtractor_vhdl;


architecture arc of FullSubtractor_vhdl is

	signal	diff	:	integer range -2 to 1;

begin

	process(X, Y, bi)
	begin
	
		diff <= X - bi - Y;
		
		if diff = -2 then		-- XYbi = 011

			D	<=	'0';
			B	<=	'1';
			
		elsif diff = -1 then	-- XYbi = 001, 010, 111
		
			D	<=	'1';
			B	<=	'1';
			
		elsif diff = 0 then		-- XYbi = 000, 101, 110
		
			D	<=	'0';
			B	<=	'0';
			
		else					-- XYbi = 100
		
			D	<=	'1';
			B	<=	'0';
			
		end if;

	
	end process;


end arc;

library ieee;
use ieee.std_logic_1164.all;


entity FullAdder2_vhdl is

	port (
		x, y, z		:	in	std_logic;
		S, C		:	out	std_logic
	);
	
end FullAdder2_vhdl;


architecture arc of FullAdder2_vhdl is

	signal nx, ny, nz	:	std_logic;

begin

	nx	<=	not x;
	ny	<=	not y;
	nz	<=	not z;

--
-- S = x'y'z + x'yz' + xy'z' + xyz
-- C = xy + xz + yz
--

	S	<=	(nx and ny and z) or
			(nx and y and nz) or
			(x and ny and nz) or
			(x and y and z);

	C	<=	(x and y ) or
			(x and z) or
			(y and z);

end arc;

--
-- VHDL을 이용한 FPGA 디지털 설계
--  3장. 조합논리 회로의 설계
--   section 02. 전가산기
--    코드 3-5	

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity FullAdder3_vhdl is

	port (
		x, y, z		:	in	integer range 0 to 1;
		S, C		:	out	std_logic
	);
	
end FullAdder3_vhdl;


architecture arc of FullAdder3_vhdl is

	signal sum	:	std_logic_vector(1 downto 0);
	
begin

	--
	-- conv_std_logic_vector 의 사용 예.
	-- 참고: conv_integer, conv_unsigned, conv_signed
	--

	process(x, y, z)
	begin
	
		sum		<=	conv_std_logic_vector(x + y + z, 2);
		
	end process;
	
	
	S	<=	sum(0);
	C	<=	sum(1);


end arc;